1. Field of the Invention
The invention relates generally to the field of high-speed digital logic circuits, and more specifically to current mode logic circuits which incorporate field effect transistors as opposed to junction transistors. The invention also provides building blocks for constructing high-speed current mode logic circuits.
2. Description of the Prior Art
Emitter coupled logic circuits, which form part of the general class of circuits known as current mode logic circuits, were first developed a number of years ago to provide extremely fast switching times in digital applications. In an emitter coupled logic circuit, a pair of high-gain transistors are used in which the emitters are connected together to form a node to which a constant current source is also connected. The current source limits the total amount of current which is permitted to flow through both transistors at any one time. The base of one of the transistors, termed here a "reference transistor", is connected to a reference voltage and the base of the other transistor, termed here an "input transistor", is connected to receive the input signal. The output signals are taken from the collector terminals of the transistors, which are connected through loads to a power supply. When the potential, or voltage, level of the input signal is significantly below that of the reference, the reference transistor is energized, or on, to conduct current. Since there is no current through the input transistor, the output signal from its collector terminal is at the voltage level of the power supply. Since current is flowing through the load connected to the reference transistor, the voltage level of the signal taken from its collector terminal is reduced from the power supply level by an amount corresponding to the voltage drop across the load. As the voltage level of the input signal increases to a point near that of the reference voltage, the input transistor also begins to turn on. As the level of the input signal rises, the input transistor conducts more current, increasing the potential level of the node controlled by the current source. Since the potential level of the node is increasing, the potential difference between the base and the emitter of the reference transistor decreases and the reference transistor begins to turn off. Eventually, the level of the input signal increases to a point at which the current through the input transistor causes the potential level of the node to, in turn, rise to a point at which the reference transistor completely turns off. In this condition, the output signal from the collector terminal of the input transistor is low, and from the output transistor of the reference transistor is high, and so the emitter-coupled logic circuit is said to have changed state.
When the input signal again falls, the reverse operation occurs, and the circuit is said to have returned to its original state. The emitter coupled logic circuit is essentially a two-state switch, with the states of the switch being reflected when the two transistors are alternately on and off.
The transistors that comprise the emitter-coupled logic circuit are generally relatively high gain, so that small changes in the voltage level of the input signal are sufficient to turn the reference transistor on and off. Accordingly, small variations in the level of the input signal around the transition level are generally sufficient to cause variations in the states of the transistors that comprise the circuit; that is, the emitter coupled logic circuits usually have relatively poor input "noise" margins. Furthermore, emitter coupled logic circuits take up more space on an integrated circuit chip, since they require the reference transistor in addition to the input transistor. Emitter coupled logic circuits also require buffer circuits such as emitter followers in their output circuits since the logic voltage levels of the output signals from the transistor pair are often shifted from the logic voltage levels of the input signals. In addition, the buffer circuits usually provide relatively small voltage differences between high (asserted) and low (negated) logic levels. Emitter-coupled logic circuits do, however, provide complementary output signals, which often can be beneficial. Furthermore, the transistors forming the circuit are kept in their unsaturated operating region, and so their switching speeds are significantly faster than have been achieved with other logic families.
The emitter coupled logic circuits naturally require junction (that is, NPN or PNP) transistors. In recent years, however, it has become desirable to use field effect transistors (FETs) in constructing digital logic circuits, particularly on integrated circuit chips. Gallium arsenide FETs have become particularly popular in high-speed switching logic, as they provide extremely fast switching times. In many circuits which incorporate field effect transistors, the bipolar transistors have often been substituted directly with field effect transistors to form the FET circuits. The FET substitution in current mode logic circuits has often led to undesirable results, however, particularly relating to the low input noise margins and low differences between voltages of the output logic levels, particularly if gallium arsenide MESFETs are used.
As has been noted, another problem with current mode logic circuits of either FETs or junction transistors is that the output voltage levels are typically shifted from the voltage levels of the input signals. While this can be taken care of by providing emitter or source followers as output buffer transistors, these often require a significant amount of space on the chip.